Electron transport properties in nanosheet MOSFETs – from assessment of optimum channel system to operation at cryogenic temperatures

This paper discusses strategies to enhance the electron mobility in nanosheet MOSFETs, particularly targeting the mobility reduction that occurs due to thickness fluctuation scattering in ultrathin body (UTB) semiconductor channels. The study proposes that channel materials with anisotropic effective masses can help mitigate this issue. Specifically, the paper explores the potential of using (111) and (100) Ge-on-Insulator (GOI) and (111) InAs-on-Insulator (InAs-OI) as promising channels for n-channel MOSFETs, focusing on their ability to reduce surface roughness scattering and enhance mobility.

The authors present a new surface roughness scattering model that accounts for non-linear scattering effects. This model predicts that materials with a light effective mass along the channel direction (mx) and a heavy effective mass perpendicular to the channel (mz) can enhance mobility. In particular, the study highlights the (100) Si and (111) Ge channels, with the L1 valleys in (111) Ge and (100) Si being especially promising due to their low subband energies.

Experimental work on UTB (100) GOI and (111) GOI channels supports the theoretical predictions. The authors show that tensile strain in (100) GOI enhances electron mobility, especially as the thickness of the GOI channel decreases. This mobility increase is attributed to the increased electron occupancy in the Δ2 valleys. Furthermore, the paper discusses how the mobility of (111) GOI and InAs-OI channels improves as their thickness approaches the 3-2 nm range, though some challenges remain, such as interface roughness in the InAs-OI devices.

The study extends to cryogenic temperatures, which are critical for cryo-CMOS operations. The authors propose a new tail state density-of-states (DOS) model to better represent the sub-threshold swing (SS) behavior at low temperatures. This model takes into account mobile and localized tail states, revealing their impact on SS and providing a better understanding of device performance at temperatures ranging from 300 K to 4 K.

In conclusion, this research provides a comprehensive framework for optimizing nanosheet MOSFETs, both at room and cryogenic temperatures, with a focus on channel material design, surface roughness scattering, and cryo-CMOS operation. The findings suggest that (100) and (111) GOI and (111) InAs-OI are promising candidates for high-performance n-MOSFETs, especially in UTB applications.