300mm fabrication of silicon quantum dot spin qubits using 0.33NA EUV lithography

This paper discusses the fabrication and performance of silicon quantum dot spin qubits using 300mm wafers and 0.33NA extreme ultraviolet (EUV) lithography. Two types of device architectures are presented: one using overlapping gates and another with a single-layer gate design, both aimed at achieving scalable and reliable qubit performance.

Key Findings:

1. Device Architectures:

• Overlapping Gates Architecture: This method involves multiple gate layers to form quantum dots. The gates are patterned using EUV lithography, achieving high precision with critical dimensions as small as 20 nm. The overlapping gates were successfully fabricated with excellent reproducibility and functional performance, demonstrated by triple quantum dot devices operating at 10 mK.

• Single-Layer Gate Architecture: A more scalable approach, the single-layer gate design reduces the complexity of patterning by using a single gate layer. This design is intended for larger qubit arrays and uses 0.33NA EUV lithography with a two-layer back-end-of-line (BEOL) process. A 3x5 trilinear array was successfully fabricated, showcasing the potential for large-scale quantum processors.

2. Fabrication Process:

• The devices were fabricated on 300mm wafers using an advanced process that involves isotopically purified silicon, high-quality silicon dioxide for gate insulation, and highly doped poly-silicon for gate material. EUV lithography was employed for the patterning of gate layers, which was critical for achieving the necessary precision and scaling of the qubit devices. SEM and TEM images confirm the successful fabrication of the devices with critical dimensions as small as 20 nm.

3. Measurement and Performance:

• Quantum Dot Functionality: Double quantum dot devices with an 80 nm dot-dot pitch were demonstrated to work effectively at room temperature, with functionality tested at 10mK in a dilution refrigerator. Charge stability maps and charge noise results were comparable to previous EBL-fabricated devices, and Rabi oscillations of both qubits were successfully controlled, indicating proper qubit operation.

• Single Qubit Performance: The devices showed coherent Rabi oscillations and good charge stability, confirming the viability of using these quantum dots for qubit operations.

4. Endurance and Reliability:

• Endurance Testing: The paper presents detailed cycling behavior and failure mechanisms of the fabricated devices. A "wake-up" process was required to initiate polarization switching in the ScAlN films, and dynamic pulsing schemes were employed to extend the endurance. The devices showed improved endurance with pulse optimization, with the top-layer devices achieving up to 10^6 cycles and the bottom-layer devices exceeding 10^7 cycles without failure. Three failure modes were identified: electrical breakdown, mechanical cracking, and ferroelectric fatigue.

5. Temperature and Overlay Performance:

• The devices were tested for temperature stability, and the resistance of critical lines was measured at both room temperature and cryogenic temperatures, showing that the resistance decreased at cryogenic temperatures, which is critical for qubit operation.

• The overlay accuracy between gate layers was maintained to within 2.5 nm (mean + 3sigma), ensuring high precision in device fabrication.

Conclusion:
The paper demonstrates the successful fabrication of scalable silicon-based quantum dot spin qubits using advanced EUV lithography. The work addresses key challenges in quantum computing, such as scaling qubits for large arrays, optimizing device performance, and improving reliability over extended cycles. The results are promising for future quantum processors, offering insights into both the operation and long-term performance of SiMOS-based spin qubit devices.