CMOS-compatible processing and room-temperature characterization at the wafer level for scalable quantum computing

This article discusses the development of a CMOS-compatible process for fabricating superconducting qubits, which is crucial for scaling up quantum processing units (QPUs) in industrial settings. The study emphasizes the use of a 200-mm wafer for qubit fabrication, focusing on methods to increase the yield and performance of qubits by conducting room-temperature (RT) characterization during the manufacturing process.

Key Points from the Article:

1. CMOS-Compatible Qubit Fabrication:

• The study presents a methodology for fabricating superconducting qubits using a CMOS-compatible process on a 200-mm wafer, utilizing industry-grade tools for high reproducibility and scalability.

• The qubits are based on Josephson junctions (JJs) formed by a double dry-etch technique, and the fabrication process is optimized for precise frequency targeting and high yield.

2. Process Control Monitoring (PCM):

• A key part of the study is the development of PCM methods, which enable real-time monitoring of the fabrication process, such as analyzing resistance and current-voltage (IV) characteristics of test structures, including junctions and shorts.

• This approach allows for early exclusion of nonfunctional devices and enables sorting of qubits based on their resistance values at RT, which correlates well with low-temperature qubit performance.

3. Wafer-Level Analysis:

• Extensive RT characterization was performed across the entire wafer, with a focus on Josephson junction (JJ) resistance, resistance variation, and the distribution of junction area and oxide barrier thickness across the wafer.

• Results showed a yield of 92.8% for functional junctions, with a resistance spread of 12.4%. The process allowed for precise control of qubit frequency targeting based on these RT measurements.

4. Cryogenic Qubit Characterization:

• Following RT characterization, the qubits were tested in cryogenic conditions using a Bluefors LD400 dilution refrigerator. Key parameters such as relaxation time (T1), dephasing time (T2*), and gate fidelity were measured.

• The qubit frequency spread was found to be 8.4%, with T1 reaching 80 µs and T2* exceeding 100 µs for the best-performing qubits, indicating high-quality devices.

5. Correlation Between RT and Cryogenic Performance:

• The RT resistance values were correlated with qubit frequencies measured at 10 mK using two-tone spectroscopy. The Ambegaokar-Baratoff formula was used to model this relationship, demonstrating the effectiveness of using RT measurements to predict cryogenic behavior.

• The study shows that the fabrication process enables precise frequency targeting for superconducting qubits, laying the groundwork for large-scale QPU development.

6. Conclusion:

• The article concludes that CMOS-compatible fabrication of superconducting qubits is a promising pathway for scaling quantum processors, with the approach demonstrating high yield, excellent frequency targeting, and superior qubit performance.

• This method is essential for advancing quantum computing architectures, particularly for the fabrication of large, multichip quantum systems, and sets the stage for future development in scalable quantum computing technology.

This work highlights the potential of combining advanced CMOS processing with quantum technology to achieve efficient and scalable qubit fabrication, which is a crucial step toward the commercialization of quantum computing.