Hybrid Channel monolithic-CFET with Si (110) pMOS and (100) nMOS

The article titled "Hybrid Channel Monolithic-CFET with Si (110) pMOS and (100) nMOS" focuses on the development of a monolithic-CFET (mCFET) that integrates different channel orientations for pMOS and nMOS devices using a single dielectric embedded middle dielectric insulator (eMDI) via layer transfer. This approach is an improvement over previous processes and aims to address scaling challenges in transistor density while improving device performance.

Key Findings

1. Monolithic-CFET (mCFET) with Hybrid Channels:

• The study presents a new monolithic-CFET architecture that uses different crystal orientations for pMOS (Si (110)) and nMOS (Si (100)) devices. This hybrid channel integration is designed to independently optimize the electron and hole mobilities, thereby improving the overall performance of the CFET.

• The approach involves integrating these devices using a single dielectric formed by layer transfer, making it easier to manage and reducing the complexity of the manufacturing process compared to previous methods like rMDI (replacement-MDI).

2. Layer Transfer and eMDI Integration:

• The process involves hydrophilic dielectric wafer fusion bonding of a carrier and donor wafer. The epitaxial CFET stack is split between the top and bottom channels, with a wafer bonding step to recombine them. The bonding dielectric acts as the middle dielectric insulator (MDI), providing flexibility in the design of the MDI thickness and allowing better control over the channel materials and device dimensions.

• By using a single dielectric for the MDI, the process reduces complexity and avoids the issues associated with selective etching of Ge-rich SiGe sacrificial layers, as seen in rMDI CFETs. Additionally, this method enhances flexibility, enabling the integration of a higher number of stacked Si channels without reaching the relaxation limits associated with epitaxial growth.

3. Device Processing and Epitaxial Growth:

• The fabrication of these devices involves nanosheet patterning using EUV lithography and a multi-step etch process to ensure precise pattern transfer through the stacked layers. The study introduces passivation steps to preserve the mask integrity and vertical profile control in heterogeneous material stacks, allowing for a more efficient etching process.

• The channel materials used include Si and SiGe, with a focus on epitaxial growth processes that maintain high-quality nanosheet structures. The SiCN bonding dielectric used for the MDI also shows potential for scaling down to future CFET nodes.

4. Electrical Performance of pMOS and nMOS:

• The study reports on the electrical performance of functional pMOS and nMOS devices featuring SiCN eMDI, with Si channels oriented along (110) for pMOS and (100) for nMOS. The performance of these devices, including their I-V characteristics, shows good functionality with minimal impact from the layer transfer process.

• For the pMOS devices on (110) Si, the performance was not as good as that of the (100) Si devices, which may be due to higher source/drain epitaxial resistance. The nMOS devices demonstrated performance close to reference devices, suggesting that the integration of different Si orientations does not negatively affect their behavior.

5. Advantages of the eMDI Approach:

• The eMDI approach offers several advantages, including easier control over the MDI thickness, the ability to independently optimize pMOS and nMOS performance, and reduced process complexity. It allows for the stacking of Si nanosheets with hybrid crystal orientations, which can help achieve better performance in both pMOS and nMOS devices.

• The reduced complexity of the process makes it more scalable and compatible with future CFET nodes, enabling high-density integration of transistors.

Conclusion

This work demonstrates a successful integration of hybrid channel orientations for pMOS and nMOS devices within a monolithic-CFET architecture using a novel eMDI process. The use of layer transfer and a single dielectric for the MDI reduces the complexity of manufacturing while enhancing the flexibility and scalability of the CFET. This approach is promising for future high-performance, high-density semiconductor devices and could play a key role in scaling transistor technology for next-generation quantum and classical computing systems.