This paper discusses the development of a hybrid monolithic channel CFET (mCFET) that integrates both p-type and n-type MOSFETs using different silicon (Si) crystal orientations for the channels. Specifically, the paper presents a new method for integrating (110) Si pMOS and (100) Si nMOS devices on a single platform using an embedded middle dielectric insulator (eMDI), which is fabricated through layer transfer techniques.
The key advantage of this approach lies in the ability to independently optimize the mobility of both p-type and n-type devices. By using Si with different crystal orientations for the pMOS and nMOS channels, the electron and hole mobilities can be enhanced separately, improving the overall performance of the CFETs. The eMDI method, as described, significantly reduces the process complexity compared to other methods like replacement-MDI (rMDI), which requires more intricate epitaxial stacks and additional layers.
The eMDI method employs hydrophilic bonding of the donor and carrier wafers to create the MDI layer, which can then be adjusted independently of the device's other layers. This process allows for better control over the thickness of the dielectric, providing flexibility in device design and scaling. Additionally, it avoids issues such as layer relaxation that could occur with more complex epitaxial growth methods. The paper also explores the impact of different plasma treatments on the bonding interface and shows that careful optimization of these treatments can reduce unwanted oxidized layers.
Device demonstrations show successful fabrication of functional (100) Si top nFET and pFETs, with promising results in terms of performance. However, the (110) Si pFET devices did not surpass their (100) Si counterparts in terms of performance, which may be attributed to the increased resistance in the source-drain epitaxial layers. This suggests that further optimization is required to fully realize the potential of the (110) Si channels.
In conclusion, the eMDI CFET integration offers a scalable and simplified method for creating high-performance transistors with heterogeneous channels, paving the way for future CFET technologies. Further development and optimization of this process, particularly for (110) Si pFETs, are necessary to achieve the desired performance improvements.
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