The paper discusses the development of a monolithically integrated optical receiver with a data rate of 1.024 Tb/s, designed for high-speed optical links using wavelength-division multiplexing (WDM). This receiver utilizes a 45nm CMOS process, featuring a 32-channel system where each channel operates at 32 Gb/s. Key innovations include the use of efficient inverse-designed grating couplers, capacitive phase shifters for wavelength alignment, and a hybrid capacitive-thermal tuning approach to ensure reliable performance despite environmental variations.
The receiver achieves exceptional energy efficiency (71 fJ/b) and bandwidth density (4 Tb/s/mm²) while maintaining a bit error rate (BER) below 10⁻¹² across all channels without the need for equalization, error correction, or digital signal processing. This energy-efficient, scalable architecture positions the receiver as a promising solution for next-generation data center interconnects, addressing the increasing demands of artificial intelligence, machine learning, and high-performance computing workloads.
The design of the photodetectors and the transimpedance amplifiers (TIAs) further optimizes the receiver's performance, minimizing crosstalk and maintaining low power consumption. The work highlights the integration of photonic and electronic components to achieve high data rates, reliability, and scalability for future optical interconnect systems in data centers.
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