Towards SoCs leveraging 200nm wafer-to-wafer interconnection pitch

This paper discusses the challenges and advancements in 3D system-on-chip (SoC) integration, focusing on interconnection technologies necessary to enable high-density, scalable architectures for modern computing systems. The study highlights the importance of system-technology co-optimization (STCO) for achieving system-level benefits and explores two key technologies for achieving 200nm wafer-to-wafer interconnection pitch: Cu-SiCN hybrid bonding and Nano Through-Silicon Vias (nTSVs).

Key Points from the Article:

1. Advancing 3D System-on-Chip (SoC) Integration:

• 3D SoC architectures are increasingly important for high-performance computing applications, as they offer enhanced density, reduced interconnect lengths, and the ability to integrate diverse technologies.

• The study investigates how to scale down 3D interconnect pitches to 250nm and 200nm, which would improve the performance of multi-threading CPUs without significantly increasing the area footprint.

2. System-Technology Co-Optimization (STCO):

• STCO is essential for addressing the challenges of scaling 3D interconnects and improving SoC performance. The study evaluates multi-threading in CPUs, where sub-micron 3D pitches could enable up to a 30% performance improvement from multi-threading without a significant area penalty.

• A physical design study using Arm 64-bit CPU sub-modules (vector processing and scheduler engines) was conducted. The results showed that 250nm 3D pitch could allow for up to 97% net completion without the need for additional circuit spacing, highlighting its potential in dense designs.

3. Cu-SiCN Hybrid Bonding Technology:

• Cu-SiCN hybrid bonding is a key enabling technology for achieving high-density wafer-to-wafer interconnects. The study demonstrates the ability to reduce interconnect pitch from 300nm to 200nm using this technology.

• The challenges associated with reducing pitch include precise control of bonding pad dimensions, which are crucial for ensuring high-density interconnects and good electrical connectivity. The technology also faces issues with Cu pad corrosion, which affects yields at smaller pitches (less than 250nm). Ongoing optimization of bonding processes is addressing these issues, improving electrical yields at 200nm pitch.

4. Nano Through-Silicon Via (nTSV) Technology:

• nTSV is another important technology for enabling fine-pitch vertical interconnections between the front and backside of wafers. This is particularly useful in creating high-density 3D interconnects.

• The study demonstrates successful implementation of nTSV technology for 210nm and 120nm pitch connections. Extreme wafer thinning is required to maintain the aspect ratio and reduce variability, and overlay control in backside lithography is crucial for accurate connections.

5. Performance and Yield Optimization:

• The study also discusses the impact of scaling down interconnect pitches on the resistance and capacitance of connections. The electrical yield decreases as the pitch decreases, mainly due to issues like Cu pad corrosion and misalignment during wafer bonding. However, optimizations in bonding processes have improved yield at smaller pitches.

• The paper provides detailed measurements of capacitance and resistance trends, showing how these parameters evolve with reduced pitch sizes, especially for nTSV and hybrid bonding connections.

6. Conclusion:

• The paper concludes that advancing 3D interconnect technologies to sub-micron pitches, particularly through hybrid bonding and nTSVs, is crucial for the future of 3D SoCs.

• These technologies enable high-density, low-power interconnects that can meet the demands of high-performance computing and multi-threading CPUs. The ongoing efforts to refine wafer-to-wafer bonding processes and optimize electrical yields are essential for the successful implementation of these technologies in future chip designs.

In summary, the paper emphasizes the need for advanced 3D interconnect technologies, such as Cu-SiCN hybrid bonding and nTSVs, to scale down interconnect pitches to 200nm and beyond, facilitating the development of high-performance, energy-efficient systems-on-chip for next-generation computing applications.