GaN Chiplet Technology Based on 300mm GaN-on-Silicon

This article introduces a groundbreaking GaN chiplet technology based on 300mm GaN-on-silicon wafers, offering significant advances in high-performance power electronics and high-speed RF applications. The work presents industry-first developments in ultra-thin GaN chiplets, monolithically integrated CMOS digital circuits, and promising reliability metrics for GaN MOSHEMTs (Metal-Oxide-Semiconductor High-Electron-Mobility Transistors).

Key Points from the Article:

1. GaN Chiplet Technology:

• The paper demonstrates the world's thinnest GaN chiplet, with an underlying silicon substrate only 19 µm thick, produced from a fully-processed, thinned, and singulated 300mm GaN-on-silicon wafer.

• The chiplet technology showcases high transistor performance and superior figure-of-merits (FoMs), such as excellent on-resistance (RON) and low gate and drain leakage.

2. Integration of CMOS Circuits:

• The paper highlights the integration of fully functional CMOS digital circuits on the same GaN chip. This includes inverters, logic gates, multiplexers, flip-flops, and ring oscillators, all implemented using a monolithically integrated GaN N-MOSHEMT and Si PMOS process.

• This integration of digital CMOS functionalities on the GaN chip enables better efficiency and high-speed switching, eliminating the need for separate CMOS companion dies.

3. GaN MOSHEMT Transistor Performance:

• The GaN MOSHEMT transistors demonstrate excellent RF performance, achieving a peak fT/fMAX of 212/304 GHz for a gate length (LG) of 30 nm.

• The study also presents the first time a high current density of ~10 A/mm² from GaN MOSHEMTs with short channel lengths (down to 30nm), which is essential for high-power applications like power electronics and RF systems.

4. Reliability Studies:

• The paper provides results from several reliability tests, including temperature-dependent dielectric breakdown (TDDB), positive bias temperature instability (pBTI), high-temperature reverse bias (HTRB), and hot-carrier injection (HCI).

• Promising results in these studies suggest that the 300mm GaN MOSHEMT technology meets the required reliability metrics, including a calculated voltage maximum (Vmax) of 1.84 V for a 10-year lifetime.

5. Ultra-Thin GaN Chiplet Fabrication:

• The fabrication process for the ultra-thin GaN chiplets involves using a stealth dicing before grinding (SDBG) process, followed by the harvesting of individual chiplets. The result is a thin, highly efficient GaN chip suitable for high-density integration in 3D packaging.

6. Potential Applications:

• The presented GaN chiplet technology is poised to advance power electronics, especially for high-density, high-performance, and energy-efficient solutions. Its integration with CMOS circuits opens the possibility for applications in power management, communications, and RF systems.

• Additionally, the technology's suitability for 3D packaging and integration into systems-on-chip (SoC) environments can enable next-generation applications in AI, RF communications, and other high-performance computing domains.

Conclusion:

This work demonstrates significant advancements in GaN-on-silicon technology, particularly in ultra-thin GaN chiplets and integrated CMOS circuits, offering promising applications in power electronics and high-speed RF systems. The GaN MOSHEMT technology shows excellent performance and reliability, making it a strong candidate for future high-density, high-efficiency power and communication applications.