Investigation and Modeling of Etching Through Silicon Carbide Vias (TSiCV) for SiC Interposer and Deep SiC Etching for Harsh Environment MEMS by DoE

The article "Investigation and Modeling of Etching Through Silicon Carbide Vias (TSiCV) for SiC Interposer and Deep SiC Etching for Harsh Environment MEMS by DoE" presents the development of dry etching processes for creating vias and deep structures in Silicon Carbide (SiC), aimed at enhancing 3-D integration for MEMS (Microelectromechanical Systems) and high-power electronics.

The research focuses on optimizing the etching process to create high-quality vias for SiC interposers and deep etched cavities for MEMS devices. The etching parameters were optimized through a Design of Experiments (DoE) approach, resulting in etch depths of up to 200 µm with an etch rate of up to 2 µm/min for via etching and up to 4 µm/min for deep etching. The process resulted in vertical sidewalls with minimal micromasking and microtrenching, crucial for high-precision MEMS devices.

The study demonstrates the feasibility of etching monocrystalline SiC with high etch rates, which is essential for MEMS applications in harsh environments. Additionally, the process was used to fabricate a 200-µm thick SiC interposer with copper metallization and a SiC MEMS device with a 50-µm thick membrane.

The findings open new avenues for 3-D integration using SiC, leveraging its superior electrical and mechanical properties, especially for applications requiring robust performance under extreme conditions such as high temperature and high voltage. The article concludes by illustrating the manufacturing of a SiC pressure sensor, highlighting the potential of SiC-based technologies for advanced electronics in demanding environments.