Soi wafer+Rapid Fabricating sub-50 nm FD-SOI

The article presents a novel method for fabricating fully depleted silicon-on-insulator (FD-SOI) wafers with sub-50 nm silicon layers using a secondary ion-cut process. FD-SOI devices are attractive for 5G, IoT, and AI applications due to their ultralow energy consumption, and achieving ultra-thin SOI layers is crucial for high-performance device scaling.

The proposed approach begins with a pre-deposited Si/SiO₂ sacrificial bilayer on a 300 mm silicon wafer, followed by hydrogen-ion implantation. This creates a hydrogen-supersaturated region that facilitates an initial (primary) ion cut at a reduced annealing temperature of 400°C, producing an as-split silicon layer approximately 100 nm thick. Despite low-temperature annealing, residual implant damage remains in the form of voids and cracks within the layer.

A subsequent secondary ion-cut step is induced during high-temperature annealing in argon (950–1050°C), which simultaneously eliminates voids and performs thermal smoothening. This step reduces the thickness of the transferred silicon layer to sub-50 nm (~40 nm) without requiring additional mechanical polishing. Transmission electron microscopy confirms a straight and smooth surface, demonstrating the method's precision. SRIM simulations also reveal the relationship between hydrogen concentration peaks and implant damage, guiding the accurate control of layer thickness and uniformity (Figures 1 and 2).

The study shows that secondary ion-cut processing, combined with careful bilayer design and controlled annealing, provides a scalable and high-precision technique for producing ultra-thin FD-SOI wafers, enabling advanced FDSOI-based devices for next-generation low-power and high-speed electronics.